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cy62167dv30 mobl ? 16-mbit (1 m 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number : 38-05328 rev. *j revised july 27, 2011 features thin small outline package (tsop-i) configurable as 1 m 16 or as 2 m 8 sram wide voltage range: 2.2 v ? 3.6 v ultra-low active power: typical active current: 2 ma at f = 1 mhz ultra-low standby power easy memory expansion with ce 1 , ce 2 and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed / power available in pb-free and non pb -free 48-ball very fine-pitch ball grid array (vfbga) and 48-pin tsop i package functional description the cy62167dv30 is a high-performance cmos static ram organized as 1m words by 16 -bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-dow n feature that significantly reduces power consumption by 99% when addresses are not toggling. the device can also be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce 1 low, ce 2 high and we low). writing to the device is accomplished by taking chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by taking chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. logic block diagram 1m 16 / 2m x 8 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 power-down circuit bhe ble ce 2 ce 1 ce 2 ce 1 a 19 byte
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 2 of 17 contents product portfolio .............................................................. 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics (over the operating range) ............................................... 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics (over the operating range) ............................................... 5 data retention waveform ................................................ 6 switching characteristics over the operating range ................................................. 6 switching waveforms ...................................................... 7 truth table ...................................................................... 11 ordering code definitions . ....................................... 12 ordering information ...................................................... 12 package diagram ............................................................ 13 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ...................................................... 15 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 3 of 17 product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1 mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max cy62167dv30ll 2.2 3.0 3.6 55 2 4 15 30 2.5 22 70 12 25 pin configuration figure 1. 48-ball vfbga top view [2, 3, 4] we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 dnu 3 2 6 5 4 1 d e b a c f g h a 16 dnu vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we ce2 dnu bhe ble a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte vss i/o15/a20 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe vss ce1 a0 48-pin tsop-i (forward) (1 m 16 / 2m 8) top view notes 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. 2. nc pins are not connected on the die. 3. dnu pins have to be left floating. 4. ball h6 for the fbga package can be used to upgrade to a 32m density. 5. the byte pin in the 48-tsop i package has to be tied to v cc to use the device as a 1m x 16 sram. the 48-ts opi package can also be used as a 2m x 8 sram by tying the byte signal to v ss . in the 2m x 8 configuration, pin 45 is a20, while bhe , ble and i/o8 to i/o14 pins are not used (dnu). [5]
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 4 of 17 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............. ............... ............... ?55 c to +125 c supply voltage to ground potential ...... ?0.2 v to v cc + 0.3 v dc voltage applied to outputs in high-z state [6, 7] ................................ ?0.2 v to v cc + 0.3 v dc input voltage [6, 7] ............................. ?0.2 v to v cc + 0.3 v output current into outputs (low) .............................. 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current ..................................................... > 200 ma operating range device range ambient temperature v cc [8] cy62167dv30ll industrial ?40 c to +85 c 2.20 v to 3.60 v electrical characteristics (over the operating range) parameter description test conditions cy62167dv30-55 cy62167dv30-70 unit min typ [9] max min typ [9] max v oh output high voltage i oh = ?0.1 ma v cc = 2.20 v 2.0 ? ? 2.0 ? ? v i oh = ?1.0 ma v cc = 2.70 v 2.4 2.4 v ol output low voltage i ol = 0.1 ma v cc = 2.20 v ? ? 0.4 ? 0.4 v i ol = 2.1 ma v cc = 2.70 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc +0.3 v 1.8 ? v cc +0.3 v v v cc = 2.7 v to 3.6 v 2.2 2.2 v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v 0.8 0.8 i ix input leakage current gnd v i v cc ?1 ? +1 ?1 ? +1 a i oz output leakage current gnd v o v cc , output disabled ?1 ? +1 ?1 ? +1 a i cc v cc operating supply current v cc = v cc(max) i out = 0 ma cmos levels f = f max = 1/t rc ? 15 30 ? 12 25 ma f = 1 mhz 2 4 2 4 i sb1 automatic power-down current ? cmos inputs ce 1 v cc ? 0.2 v or ce 2 0.2 v, v in v cc ? 0.2 v, v in 0.2 v, f = f max (address and data only), f = 0 (oe , we ), v cc = 3.60 v ? 2.5 22 ? 2.5 22 a i sb2 automatic power-down current ? cmos inputs ce 1 v cc ? 0.2 v or ce 2 0.2 v v in v cc ? 0.2 v or v in 0.2v, f = 0, v cc = 3.60 v ? 2.5 22 ? 2.5 22 a notes 6. v il(min.) = ?2.0 v for pulse durations less than 20 ns. 7. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 8. full device ac operation requires linear v cc ramp from 0 to v cc(min.) and v cc must be stable at v cc(min) for 500 s. 9. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 5 of 17 capacitance parameter [10] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 8pf c out output capacitance 10 pf thermal resistance parameter [10] description test conditions vfbga tsop i unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, 2-layer printed circuit board 55 60 c / w jc thermal resistance (junction to case) 16 4.3 c / w ac test loads and waveforms v cc v cc output r2 50 pf [12] including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: the venin equivalent all input pulses r th r1 parameters 2.5 v 3.0 v unit r1 16667 1103 r2 15385 1554 r th 8000 645 v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min typ [11] max unit v dr v cc for data retention 1.5 ? ? v i ccdr data retention current v cc = 1.5 v, ce 1 v cc ? 0.2 v or ce 2 0.2 v, v in v cc ? 0.2 v or v in 0.2 v ??10 a t cdr [10] chip deselect to data retention time 0 ? ? ns t r [12] operation recovery time cy62167dv30ll-55 55 ? ? ns cy62167dv30ll-70 70 notes 10. tested initially and after any design or proc ess changes that may affect these parameters. 11. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c 12. full device operation requires linear v cc ramp from v dr to v cc(min.) 100 s or stable at v cc(min.) 100 s.
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 6 of 17 data retention waveform [13] switching characteristics over the operating range parameter [14] description 55 ns 70 ns unit min max min max read cycle t rc read cycle time 55 ? 70 ? ns t aa address to data valid ? 55 ? 70 ns t oha data hold from address change 10 ? 10 ? ns t ace ce 1 low and ce 2 high to data valid ? 55 ? 70 ns t doe oe low to data valid ? 25 ? 35 ns t lzoe oe low to low z [15] 5? 5 ? ns t hzoe oe high to high z [15, 16] ?20 ? 25 ns t lzce ce 1 low and ce 2 high to low z [15] 10 ? 10 ? ns t hzce ce 1 high and ce 2 low to high z [15, 16] ?20 ? 25 ns t pu ce 1 low and ce 2 high to power-up 0 ? 0 ? ns t pd ce 1 high and ce 2 low to power-down ? 55 ? 70 ns t dbe ble/bhe low to data valid ? 55 ? 70 ns t lzbe ble /bhe low to low z [15] 10 ? 10 ? ns t hzbe ble /b he high to high z [15, 16] ?20 ? 25 ns write cycle [17] t wc write cycle time 55 ? 70 ? ns t sce ce 1 low and ce 2 high to write end 40 ? 60 ? ns t aw address setup to write end 40 ? 60 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 40 ? 45 ? ns t bw ble /bhe low to write end 40 ? 60 ? ns t sd data setup to write end 25 ? 30 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe we low to high-z [15, 16] ?20 ? 25 ns t lzwe we high to low-z [15] 10 ? 10 ? ns notes 13. bhe .ble is the and of both bhe and ble . chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble . 14. test conditions for all parameters other than tri-state paramet ers assume signal transition time of 1 ns/v, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 15. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 16. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 17. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that terminates the write. v cc , min. v cc , min. t cdr v dr 1.5 v data retention mode t r ce 1 or v cc bhe , ble or ce 2
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 7 of 17 switching waveforms figure 2. read cycle 1 (a ddress transition controlled) [18, 19] figure 3. read cycle 2 (oe controlled) [19, 20] notes 18. the device is continuously selected. oe , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . 19. we is high for read cycle. 20. address valid prior to or coincident with ce 1 , bhe , ble transition low and ce 2 transition high. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzbe t lzbe t hzce t dbe high i cc i sb impedance oe ce 1 address v cc supply current bhe /ble data out ce 2
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 8 of 17 figure 4. write cycle 1 (we controlled) [21, 22, 23] notes 21. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can termina te a write by going inactive. the data input setup and hold timing should be refere nced to the edge of the signal that terminates the write. 22. data i/o is high-impedance if oe = v ih . 23. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high-impedance state. 24. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data t bw see note 24 address we data i/o oe bhe /ble ce 1 ce 2
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 9 of 17 figure 5. write cycle 2 (ce 1 or ce 2 controlled) [25, 26, 27] figure 6. write cycle 3 (we controlled, oe low) [27] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data note 28 t bw t sa ce 1 address we data i/o oe bhe /ble ce 2 valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 28 ce 1 address ce 2 we data i/o bhe /ble notes 25. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , bhe and/or ble = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be refere nced to the edge of the signal that terminates the write. 26. data i/o is high-impedance if oe = v ih. 27. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high-impedance state. 28. during this period, the i/os are in output state and input signals should not be applied.
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 10 of 17 figure 7. write cycle 4 (bhe /ble controlled, oe low) [29] switching waveforms (continued) t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe note 30 data i/o address ce 1 we bhe /ble ce 2 notes 29. if ce 1 goes high and ce 2 goes low simultaneously with we = v ih , the output remains in a high-impedance state. 30. during this period, the i/os are in output state and input signals should not be applied.
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 11 of 17 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x x x x x high z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l high z (i/o 8 ?i/o 15 ); data out (i/o 0 ?i/o 7 ) read active (i cc ) l h h l l h data out (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) read active (i cc ) lhlxlldata in (i/o 0 ?i/o 15 ) write active (i cc ) lhlxhlhigh z (i/o 8 ?i/o 15 ); data in (i/o 0 ?i/o 7 ) write active (i cc ) lhlxlhdata in (i/o 8 ?i/o 15 ); high z (i/o 0 ?i/o 7 ) write active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc )
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 12 of 17 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 55 cy62167dv30ll-55bvi 51-85178 48-ball fbga (8 9.5 1 mm) industrial cy62167dv30ll-55bvxi 48-ball fbga (8 9.5 1 mm) (pb-free) cy62167dv30ll-55zxi 51-85183 48-pin tsop-i (12 18.4 1 mm) (pb-free) 70 cy62167dv30ll-70bvi 51-85178 48-ball fbga (8 9.5 1 mm) please contact your local cypress sales re presentative for availability of these parts cy 621 6 7d ll xx xxx i company id: cy = cypress mobl sram family density = 16 mbit bus width = x16 d = 130nm technology speed grade package type = zx : tsop i (pb-free) bvx : vfbga (pb-free) bv : vfbga temperature grades i = industrial low power v30 voltage = 3.0
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 13 of 17 package diagram figure 8. 48-ball vfbga (8 9.5 1 mm) (51-85178) 51-85178 *a
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 14 of 17 figure 9. 48-pin tsop-i (12 18.4 1 mm) (51-85183) 51-85183 *c
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 15 of 17 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor i/o input/output sram static random access memory vfbga very fine ball grid array tsop thin small outline package symbol unit of measure c degrees celsius a microampere ma milliampere mhz megahertz ns nanosecond pf picofarad v volt ohm w watts
cy62167dv30 mobl ? document number : 38-05328 rev. *j page 16 of 17 document history page document title: cy62167dv30 mobl ? , 16-mbit (1 m 16) static ram document number: 38-05328 revision ecn orig. of change submission date description of change ** 118408 gug 09/30/02 new datasheet *a 123692 dpm 02/11/03 changed advanced to preliminary added package diagram *b 126555 dpm 04/25/03 minor change: changed sunset owner from dpm to hrt *c 127841 xrj 09/10/03 added 48 tsop i package *d 205701 aju changed byte pin usage description for 48 tsopi package *e 238050 kkv/aju see ecn replaced 48-ball vfbga package diagram; modified package name in ordering information table from bv48a to bv48b *f 304054 pci see ecn added 45-ns speed bin in ac, dc and ordering information tables added footnote #12 on page #4 added pb-free packages on page # 10 *g 492895 vkn see ecn modified datasheet to explain x8 configurability. removed l power bin from the product offering updated ordering information table *h 2896036 aju 03/19/10 removed 45-ns. removed inactive parts from ordering information. updated packaging information updated links in sales, solutions, and legal information. *i 3067267 rame 11/08/10 updated datasheet as per new template added ordering code definitions , acronyms and units of measure . updated all table notes to footnote. package diagram updated 51-85178 from ** to *a *j 3329789 rame 07/27/11 removed references to an1064 sram system guidelines. updated template according to current cy standards.
document number : 38-05328 rev. *j revised july 27, 2011 page 17 of 17 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor corporation. all product and compa ny names mentioned in this document may be the trademarks of their respective holders. cy62167dv30 mobl ? sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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